The invention relates generally to system clocking in computer systems, particularly it relates to system clocking in connected network computer systems with an enhanced degree of performance and reliability. Even more particularly, it relates to a method for hot-switching, i.e., hot-plugging between a first and a second clock signal used to supply a computer system with clock information, in which said second signal is a stand-by signal for said computer system.
The present invention has a broad field of application, which includes any computer system having an operating clock and any requirement for hot-switching to a second clock supply in case of a failure or just a recognizable trend to a failure or insufficient operation of any piece of software or hardware being used to supply the first clock. Thus it can be applied in a large range of computer systems from a single stand-alone PC, or any computing device being even smaller than a PC to larger systems, in particular mainframe systems and even more particularly to a high-end system of inter-connected high-performance integrated system clusters in which each cluster comprises a plurality of central electronic complexes further referred to herein as CEC, e.g., some arrangement of high performance mainframe computer and its associated environment.
The present invention will be described with particular respect to such high-end systems which need such characterizing features, although its scope is as indicated above. In such high-end systems, the application work is distributed all over the plurality of CECs in multiple clusters. For achieving good performance the clusters are connected via high-speed optical fiber cables.
Especially in highly sophisticated applications running in such systems, which applications have a great need for system stability and reliability (like banking applications and the like), a proper operation of such a clustered application needs precisely synchronized and reliably supplied time information in order to have the same time base everywhere in the plurality of clusters. In spite of enhanced security requirements the essential system resources (like e.g. the clocking information) of such systems are provided redundantly.
Such a system is described with its requirements concerning the time facility in IBM Journal Of Research and Development, Vol.36, No.4, July 1992, p. 658. Here it is expressed that such a tough requirement of system availability implies that the possibility to maintain a plurality of xe2x80x98distributedxe2x80x99 time sources in each CEC, for example, is excluded. Thus, one central time information supplier is needed for the whole system.
As indicated above some degree of clock supplier failure safety is required. Thus, at least two redundant time information suppliers, further exemplarily referred to herein as Sysplex Timers (ST) as they are called in IBM S/390 systems are required. Each ST is in turn connected with an external absolute time source further referred to as ETS, such as Global Positioning System (GPS) time source or the like. Said two STs are connected with the system via particular, dedicated high speed cables. Such a type of system is depicted in FIG. 1 where two clusters are depicted, each with a respective ST. To a given time only one of said time sources supplies the plurality of CECs with time information. Time information is synchronized between the two time sources with a dedicated time information line, again. On a failure in said xe2x80x98activexe2x80x99 time source the other (i.e., stand-by time source) replaces the operation of the first.
The most critical apparatus in the clock supply chain is often a transceiver which converts optical signals into electrical signals. Such transceiver element is not depicted explicitly in FIG. 1 but can be considered as part of said ISC links 18. The oscillators themselves are quite failure safe compared to the transceivers. The present invention""s concept can be applied particularly in systems like that shown in FIG. 1 when any element in said supply chainxe2x80x94particularly said transceiverxe2x80x94should fail, but the clock signals are still detectable upstream of said element which failed. Such an interruption of system operation should be avoided for a variety of reasons.
The most important obstacle on the way to hot-switching systems from one clocking source to any stand-by clocking source is that a proper switching requires nearly a perfect phase coincidence in both clock signals having freely moving phase fronts relative to one another. Such tough requirements exist due to sensitive PLL circuits arranged for generating the desired system clock of several 100 Mhz. Sensitive PLL circuits need an accuracy of about 20 picoseconds in phase coincidence. Such an accuracy, however, could not be achieved until now as the simplest logic comprising an AND or an OR gate will generate a delay of already nearly 100 pico seconds.
It is thus the object of the present invention, to overcome these difficulties and to provide a method and system for switching between two high frequency signals, in particular between two high frequency clocking sources which are able to meet said tough requirements of phase coincidence mentioned above.
The foregoing and other objects of the invention are achieved by the features stated in enclosed independent claims. Further advantageous arrangements and embodiments of the invention are set forth in the respective subclaims.
The basic idea comprising the present invention is to observe the two clocking phase signals and find out a point in time when said signals have a phase coincidence which is good enough for fulfilling said requirement of e.g. 20 ps phase differencexe2x80x94and then switch from one clock source to the other. The essential idea is not to compare the phases directly but to generate an auxiliary signal out of the two clock signals which is easier to handle in order to find that desired point in time and which reflects all desired properties of the time dependent phase shift between said clock signals.
The auxiliary xe2x80x98phase detectorxe2x80x99 signal is generated as follows: at a predetermined location in the cycle of both clock signals (e.g. at its positive transition) a pulse is generated out of each of the clock signals with matched identical delay elements located very close to each other on the same chip for both signals. As they match they produce exactly the same pulse widths. The absolute length of the pulse width is of minor relevance as long as the length of the pulses is the same within close limits. Both signals are ANDed. Thus, in the resulting signal a pulse emerges at every positive transition of the oscillator clocks when the phase alignment of the clock signals is closer than the width of the transition pulse. When the alignment is bad, no signal will be produced.
In particular, said ANDed signal emerges from a small spike, grows to the width of the transition pulses, indicating perfect phase alignment, shrinks again to a small spike, and then disappears for a while before it emerges again in the same manner.
Thus, with the ANDed signal, a xe2x80x98phase coincidence signalxe2x80x99 is found which varies its characteristics with a frequency which is orders of magnitudes smaller than that of the clock signals and can thus be far easier evaluated. In the wording of the appended claims the evolution of said signal is characterized by a sequence of signatures varying in time (from no signal to small spike, larger spike, pulse having the width of the transition pulse, large spike, small spike, and again to no signal) which reflects the xe2x80x98subsequent occurrence of the phase coincidence signalxe2x80x99.
Now, a broad variety of possibilities exist to evaluate said ANDed signal. Advantageously, only the begin and the end of time intervals must be determined to which a predetermined desired level of phase coincidence is existent or exceeded. Then, the center of said time interval can be chosen for the trigger time in which the hot-switching will be performed.
In a preferred embodiment of the present invention the above method is implemented with a simple phase detector logic and only two counters. The trigger time is determined by the occurrence of a counter overflow, generating a trigger signal which drives a select latch for switching from one clock to the other to an optimum point in time.
Thus, the present invention discloses a simple method and system for hot-switching between two clock signals which are simply to be realized without any larger efforts im programming logic and with small consumption of system resources. Finally, the proposed solution is a low cost solution.
The inventive concept is applicable to distributed systems having a central clock supply and to future systems having distributed clock sources, i.e. in the CECs where they are needed.
Instead of a clock signal, in general, other high frequency signals can be switched, too, (e.g. any relevant high frequency signal which is usable in a double form, one being an active, the other being a stand-by form).